Memory is widely utilized and often embedded into an integrated circuit as discrete blocks of memory that can be cascaded. There are a number of methods for cascading the memory blocks in an integrated circuit, such as for example in a programmable logic device (PLD). For example, one approach is to utilize the PLD's general purpose routing fabric to propagate memory address, data, and control signals along the memory blocks. This approach has the advantage of requiring no dedicated address bus or data bus for cascading, but severe routing congestion may occur (e.g., near the interface of the memory block and logic cells within the PLD to such an extent that routing resources for cascading may not always be available).
Another approach utilizes a dedicated address bus and data bus for the memory blocks (e.g., running along the entire length of the embedded memory row or column), with the address and data lines buffered at regular intervals (e.g., buffers with tri-state controls to allow bi-directional cascading without contention). The dedicated buses and associated circuitry for cascading, however, increase the required die area and PLD cost and may not be utilized at all if cascading is not desired. As a result, there is a need for improved techniques for cascading memory.